From High-level Descriptions to VLSI Circuits
نویسندگان
چکیده
منابع مشابه
Delay Estimation of VLSI Circuits from a High-Level View†
Estimation of the delay of a Boolean function from its functional description is an important step towards design exploration at the register transfer level (RTL). This paper addresses the problem of estimating the delay of certain optimal multi-level implementations of combinational circuits, given only their functional description. The proposed delay model uses a new complexity measure called...
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A novel full design and test generation system with combined High-Level Synthesis (HLS) and automated Hierarchical Test Pattern Generation (HTPG) was developed and experimented in cooperation between Linköping University and Tallinn Technical University. The high-level synthesis is based on an internal model of Extended Timed Petri Net (ETPN) representations. In the test generator both, registe...
متن کاملDelay Estimation of VLSI Circuits from a High - Level View 1
Estimation of the delay of a Boolean function from its functional description is an important step towards design exploration at the register transfer level (RTL). This paper addresses the problem of estimating the delay of certain op t ima l multi-level implementations of combinational circuits, given only their functional description. The proposed delay model uses a new complexity measure cal...
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ژورنال
عنوان ژورنال: DAIMI Report Series
سال: 1988
ISSN: 2245-9316,0105-8517
DOI: 10.7146/dpb.v17i255.7610